1 data sheet acquired from harris semiconductor schs164f features four operating modes - shift right, shift left, hold and reset synchronous parallel or serial operation typical f max = 60mhz at v cc = 5v, c l = 15pf, t a = 25 o c asynchronous master reset fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh pinout cd54hc194 (cerdip) cd74hc194 (pdip, soic, sop, tssop) cd74hct194 (pdip) top view description the ?c194 and cd74hct194 are 4-bit shift registers with asynchronous master reset ( mr). in the parallel mode (s0 and s1 are high), data is loaded into the associated ?p-?p and appears at the output after the positive transition of the clock input (cp). during parallel loading serial data ?w is inhibited. shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (dsl) serial input for the shift right mode, and at the shift right (dsr) serial input for the shift left mode. clearing the register is accomplished by a low applied to the master reset ( mr) pin. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 mr dsr d 0 d 1 d 2 d 3 gnd dsl v cc q 1 q 2 q 3 cp s1 s0 q 0 ordering information part number temp. range ( o c) package cd54hc194f3a -55 to 125 16 ld cerdip cd74hc194e -55 to 125 16 ld pdip cd74hc194m -55 to 125 16 ld soic cd74hc194mt -55 to 125 16 ld soic cd74hc194m96 -55 to 125 16 ld soic cd74hc194nsr -55 to 125 16 ld sop cd74hc194pw -55 to 125 16 ld tssop cd74hc194pwr -55 to 125 16 ld tssop cd74hc194pwt -55 to 125 16 ld tssop CD74HCT194E -55 to 125 16 ld pdip note: when ordering, use the entire part number. the suf?es 96 and r denote tape and reel. the suf? t denotes a small-quantity reel of 250. september 1997 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc194, cd74hc194, cd74hct194 high-speed cmos logic 4-bit bidirectional universal shift register [ /title ( cd74 h c194, c d74h c t194) / sub- j ect ( high- s peed c mos l ogic 4 -bit
2 functional diagram truth table operating mode inputs output cp mr s1 s0 dsr dsl d n q 0 q 1 q 2 q 3 reset (clear) x l x x x x x llll hold (do nothing) x h l (note 1) l (note 1) x x x q 0 q 1 q 2 q 3 shift left h h l (note 1) x l x q 1 q 2 q 3 l h h l (note 1) x h x q 1 q 2 q 3 h shift right h l (note 1) h l x x l q 0 q 1 q 2 h l (note 1) h h x x h q 0 q 1 q 2 parallel load hh hxxd n d 0 d 1 q 2 d 3 h = high voltage level, h = high voltage level one set-up time prior to the low to high clock transition, l = low voltage level, l = low voltage level one set-up time prior to the low to high clock transition, d n (q n ) = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the low to high clock transition, x = don? care, = transition from low to high level note: 1. the high-to-low transition of the s0 and s1 inputs on the ?c194 and cd74hct194 should take place only while cp is high for conventional operation. 14 12 13 15 q 0 q 1 q 2 q 3 7 6 3 4 5 d 0 d 1 d 2 d 3 gnd = 8 v cc = 16 2 9 10 1 11 dsl dsr s0 s1 mr cp cd54hc194, cd74hc194, cd74hct194
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) package thermal impedance, ja (see note 2): e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 o c/w m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 o c/w ns (sop) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 o c/w pw (tssop) package . . . . . . . . . . . . . . . . . . . . . . . . . 108 o c/w maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 2. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v cd54hc194, cd74hc194, cd74hct194
4 input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc to gnd 0 5.5 - - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 a additional quiescent device current per input pin: 1 unit load ? i cc (note 3) v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 3. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads cp 0.6 mr 0.55 dsl, dsr, d n 0.25 sn 1.10 note: unit load is ? i cc limit speci?d in dc electrical speci?ations table, e.g. 360 a max at 25 o c. cd54hc194, cd74hc194, cd74hct194
5 prerequisite for switching function parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min max min max min max hc types max. clock frequency (figure 1) f max - 26-5-4-mhz 4.5 30 - 24 - 20 - mhz 6 35 - 28 - 23 - mhz mr pulse width (figure 2) t w - 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 614-17-20-ns clock pulse width (figure 1) t w - 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 614-17-20-ns set-up time data to clock (figure 3) t su - 2 70 - 90 - 105 - ns 4.5 14 - 18 - 21 - ns 612-15-19-ns removal time, mr to clock (figure 2) t rem - 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 610-13-15-ns set-up time s1, s0 to clock (figure 4) t su - 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 614-17-20-ns set-up time dsl, dsr to clock (figure 4) t su - 2 70 - 90 - 105 - ns 4.5 14 - 18 - 21 - ns 612-15-18-ns hold time s1, s0 to clock (figure 4) t h - 20-0-0-ns 4.50-0-0-ns 60-0-0-ns hold time data to clock (figure 3) t h - 20-0-0-ns 4.50-0-0-ns 60-0-0-ns hct types max. clock frequency (figure 1) f max - 4.5 27 - 22 - 18 - mhz mr pulse width (figure 2) t w - 4.5 16 - 20 - 24 - ns clock pulse width (figure 1) t w - 4.5 16 - 20 - 24 - ns set-up time, data to clock (figure 3) t su - 4.5 14 - 18 - 21 - ns removal time mr to clock (figure 2) t rem - 4.5 12 - 15 - 18 - ns cd54hc194, cd74hc194, cd74hct194
6 set-up time s1, s0 to clock (figure 4) t su - 4.5 20 - 25 - 30 - ns set-up time dsl, dsr to clock (figure 4) t su - 4.5 14 - 18 - 21 - ns hold time s1, s0 to clock (figure 4) t h - 4.50-0-0-ns hold time data to clock (figure 3) t h - 4.50-0-0-ns switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units typ max max max hc types propagation delay, clock to output (figure 1) t plh , t phl c l = 50pf 2 - 175 220 265 ns 4.5 - 35 44 53 ns 6 - 30 37 45 ns propagation delay, clock to q t plh , t phl - 5 14 - - - ns output transition time (figure 1) t tlh , t thl c l = 50pf 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns propagation delay, mr to output (figure 2) t phl c l = 50pf 2 - 140 175 210 ns 4.5 - 28 35 42 ns 6 - 24 30 36 ns input capacitance c in ---1010 10pf maximum clock frequency f max - 5 60 - - - mhz power dissipation capacitance (notes 4, 5) c pd - 5 55 - - - pf hct types propagation delay, clock to output (figure 1) t plh , t phl c l = 50pf 4.5 - 37 46 56 ns propagation delay, clock to q t plh , t phl - 5 15 - - - ns output transition times (figure 1) t tlh , t thl c l = 50pf 4.5 - 15 19 22 ns propagation delay, mr to output (figure 2) t phl c l = 50pf 4.5 - 40 50 60 ns input capacitance c in ---1010 10pf maximum clock frequency f max - 5 50 - - - mhz power dissipation capacitance (notes 4, 5) c pd - 5 60 - - - pf notes: 4. c pd is used to determine the dynamic power consumption, per gate. 5. p d = v cc 2 f i + (c l v cc 2 ) where f i = input frequency, c l = output load capacitance, v cc = supply voltage. prerequisite for switching function (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min max min max min max
7 test circuits and waveforms figure 1. clock prerequisite times and propagation and output transition times figure 2. master reset prerequisite times and propagation delays figure 3. data prerequisite times figure 4. parallel load or shift-left/shift-right prerequisite times i nput level cp t r v s q t thl t tlh 10% 90% gn d v s v s 90% t phl t w v s 10% 10% t f t plh v s mr v s v s input level gnd t rem v s input level gnd cp q t phl v s t w data cp t su v s valid t h v s input level input level gnd gnd valid s or ds v s t su t h v s cp input level gnd input level gnd
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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